For conventional image sensor packages, substrates are implemented as carriers for image sensor chips as revealed in U.S. Pat. No. 7,005,720 taught by Huang etc. An image sensor chip is disposed on a substrate and is electrically connected to the substrate by a plurality of bonding wires. Dam is disposed on the peripheries of the substrate and a transparent lid is disposed on the dam so that the image sensor chip is airtight sealed inside the space formed by the substrate, the lid, and the dam. Therefore, a conventional substrate footprint is at least four times larger than the image sensor chip. However, as the requirements of smart phones or portable devices for light, thin, small with more functions, the image sensor packages need further microminiaturization.
As the development of image sensor package moving toward chip scale packages, the formation and location of dam become crucial for better product reliability. If the dam is formed on a CMOS chip by printing, the location tolerance of the dam is too large where the image sensing area of an image sensor chip is easily contaminated during dam formation processes. Moreover, too large or too small opening of the image sensing window formed by the dam may cause product defeats. When the image sensing window is a large opening, the transparent lid is easily come off due to less adhesive area between the dam and the transparent lid. On the other hand, when the image sensing window is a small opening, residues of the dam during formation processes is disposed on the corners and peripheries of the image sensing window leading to poor sensing performance. Moreover, for a dam with more than 40 μm thickness, the current bottleneck for the horizontal spacing from the peripheries of the image sensing window to the image sensing area of an image sensing chip has to be greater than 200 μm to achieve better CSP package reliability where image sensor chips cannot further be reduced and microminiaturized.